![]() ![]() Dandapat, Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit. Srinivasa Rao, Implementation of low power one-bit full adder with cadence tool. Mirzakuchaki, Design and analysis of a novel low-power and energy-efficient 18T hybrid full adder. Lau, Approximate adder for low-power computations. Linares-Aranda, CMOS full-adders for energy-efficient arithmetic applications. 2005 18th Symposium on Integrated Circuits and Systems Design, 166–171 2005 Linares, in An alternative logic approach to implement high-speed low-power full adder cells. This ensures that the proposed adder outperforms the traditional design and the state of the artwork. The full adder has a 12.99% power reduction over the existing low-power adder and a 58.4% power reduction over the 28 transistors. The proposed design has been compared against the various full and approximate adders. Further, the full adder has been extended as an adder/subtractor unit of 4 bits, with the power delay product as 0.1285 × 10 − 18 J for the critical delay of 1.095 ns. Pre- and post-layout simulations evidence the accuracy of the results in which the design consumes 1.843 µW of power with 0.605 ns as the worst-case delay on 90 nm technology. The proposed full adder design has been constructed against ten different complementary metal oxide semiconductor processing technologies, namely 0.6 µm, 0.8 µm, 0.12 µm, 1.2 µm, 0.18 µm, 0.25 µm, 0.35 µm, 50 nm, 70 nm and 90 nm. The combination of the GDI and PTL brings a novelty to the full adder circuit, through which the design required only 10 transistors to perform adding operations. In contrast, the gate diffusion input (GDI) technique has been used to alter the multiplexer design. The proposed full adder has one XOR gate and two 2:1 multiplexers in which the XOR gate has been customised with 4 transistors using pass transistor logic (PTL). A traditional full adder with 28 transistors has been devised with 10 transistors of an equal amount of PMOS and NMOS, guaranteeing the proper switching activity. The general focus of this work is to design an area-optimised full adder and utilise it to lay out a low-power arithmetic unit that can be helpful for microprocessors. ![]()
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